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? semiconductor components industries, llc, 2014 june, 2014 ? rev. 19 1 publication order number: mc10ep195/d mc10ep195, mc100ep195 3.3v ecl programmable delay chip the mc10/100ep195 is a programmable delay chip (pdc) designed primarily for clock deskewing and timing adjustment. it provides variable delay of a differential necl/pecl input transition. the delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, figure 3. the delay increment of the ep195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. the required delay is selected by the 10 data select inputs d[9:0] values and controlled by the len (pin 10). a low level on len allows a transparent load mode of real time delay values by d[9:0]. a low to high transition on len will lock and hold current values present against any subsequent changes in d[10:0]. the approximate delay values for varying tap numbers correlating to d0 (lsb) through d9 (msb) are shown in table 6 and figure 4. because the ep195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. an additional pin d10 is provided for controlling pins 14 and 15, cascade and cascade , also latched by len, in cascading multiple pdcs for increased programmable range. the cascade logic allows full control of multiple pdcs. switching devices from all ?1? states on d[0:9] with setmax low to all ?0? states on d[0:9] with setmax high will increase the delay equivalent to ?d0?, the minimum increment. select input pins d[10:0] may be threshold controlled by combinations of interconnects between v ef (pin 7) and v cf (pin 8) for lvcmos, ecl, or lvttl level signals. for lvcmos input levels, leave v cf and v ef open. for ecl operation, short v cf and v ef (pins 7 and 8). for lvttl level operation, connect a 1.5 v supply reference to v cf and leave open v ef pin. the 1.5 v reference voltage to v cf pin can be accomplished by placing a 2.2 k resistor between v cf and v ee for a 3.3 v power supply. the v bb pin, an internally generated voltage supply, is available to this device only. for single?ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? maximum input clock frequency >1.2 ghz typical ? programmable range: 0 ns to 10 ns ? delay range: 2.2 ns to 12.2 ns ? 10 ps increments ? pecl mode operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?3.0 v to ?3.6 v ? open input default state ? safety clamp on inputs ? a logic high on the en pin will force q to logic low ? d[10:0] can accept either ecl, lvcmos, or lvttl inputs ? v bb output reference voltage ? these are pb?free devices 32 1 lqfp?32 fa suffix case 873a marking diagram* xxx = 10 or 100 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package *for additional marking information, refer to application note and8002/d. mcxxx ep195 awlyywwg http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information qfn32 mn suffix case 488am 32 1 mcxxx ep195 awlyyww 1 (note: microdot may be in either location)
mc10ep195, mc100ep195 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 v ee d0 v cc q q nc v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf figure 1. 32?lead lqfp pinout (top view) mc10ep195 mc100ep195 32 31 30 29 28 27 26 25 9 10 11 12 1314 1516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 figure 2. 32?lead qfn (top view) v bb in d8 v ef d9 d10 in v cf d2 d1 v ee d3 d4 d5 d6 d7 v ee d0 v cc q q nc v cc v cc cascade en setmax v cc v ee len cascade setmin exposed pad (ep)
mc10ep195, mc100ep195 http://onsemi.com 3 table 1. pin description pin name i/o default state description 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 d[0:9] lvcmos, lvttl, ecl input low single?ended parallel data inputs [0:9]. internal 75 k to v ee . (note 1) 3 d[10] lvcmos, lvttl, ecl input low single?ended cascade/cascade control input. internal 75 k to v ee . (note 1) 4 in ecl input low noninverted differential input. internal 75 k to v ee . 5 in ecl input high inverted differential input. internal 75 k to v ee and 36.5 k to v cc . 6 v bb ? ? ecl reference voltage output 7 v ef ? ? reference voltage for ecl mode connection 8 v cf ? ? lvcmos, ecl, or lvttl input mode select 9, 24, 28 v ee ? ? negative supply voltage. all v ee pins must be externally connected to power supply to guarantee proper operation. (note 2) 13, 18, 19, 22 v cc ? ? positive supply voltage. all v cc pins must be externally connected to power supply to guarantee proper operation. (note 2) 10 len ecl input low single?ended d pins load / hold input. internal 75 k to v ee . 11 setmin ecl input low single?ended minimum delay set logic input. internal 75 k to v ee . (note 1) 12 setmax ecl input low single?ended maximum delay set logic input. internal 75 k to v ee . (note 1) 14 cascade ecl output ? inverted differential cascade output for d[10]. typically terminated with 50 to v tt = v cc ? 2 v. 15 cascade ecl output ? noninverted differential cascade output. for d[10] typically terminated with 50 to v tt = v cc ? 2 v. 16 en ecl input low single?ended output enable pin. internal 75 k to v ee . 17 nc ? ? no connect. the nc pin is electrically connected to the die and ?must be? left open 21 q ecl output ? noninverted differential output. typically terminated with 50 to v tt = v cc ? 2 v. 20 q ecl output ? inverted differential output. typically terminated with 50 to v tt = v cc ? 2 v. 1. setmin will override setmax if both are high. setmax and setmin will override all d[0:10] inputs. 2. all v cc and v ee pins must be externally connected to power supply to guarantee proper operation.
mc10ep195, mc100ep195 http://onsemi.com 4 table 2. control pin pin state function en low (note 3) input signal is propagated to the output high output holds logic low state len low (note 3) transparent or load mode for real time delay values present on d[0:10]. high lock and hold mode for delay values on d[0:10]; further changes on d[0:10] are not recognized and do not affect delay. setmin low (note 3) output delay set by d[0:10] high set minimum output delay setmax low (note 3) output delay set by d[0:10] high set maximum output delay d10 low (note 3) cascade output low, cascade output high high cascade output low, cascade output high 3. internal pulldown resistor will provide a logic low if pin is left unconnected. table 3. control d[0:10] interface v cf v ef pin (note 4) ecl mode v cf no connect lvcmos mode v cf 1.5 v 100 mv lvttl mode (note 5) 4. short v cf (pin 8) and v ef (pin 7). 5. when operating in lvttl mode, the reference voltage can be provided by connecting an external resistor, r cf (suggested resistor value is 2.2 k 5%), between v cf and v ee pins. table 4. data input allowed operating voltage mode table power supply control data select inputs pins (d [0:10]) lvcmos lvttl lvpecl lvnecl pecl mode operating range yes yes yes n/a necl mode operating range n/a n/a n/a yes table 5. attributes characteristics value internal input pulldown resistor (r1) 75 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 6) pb?free pkg lqfp?32 level 2 qfn?32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 1217 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 6. for additional information, see application note and8003/d.
mc10ep195, mc100ep195 http://onsemi.com 5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 in in 512 gd* 0 1 256 gd* 0 1 128 gd* 0 1 64 gd* 0 1 32 gd* 0 1 16 gd* 0 1 8 gd* 0 1 4 gd* 0 1 2 gd* 0 1 1 gd* 0 1 1 gd* 0 1 1 gd* 0 1 latch cascade cascade q q en len set min set max 10 bit latch d10 *gd = (gate delay) approximately 10 ps delay per gate (minimum fixed delay approx. 2.2 ns) v bb v cf v ef figure 3. logic diagram v ee r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1
mc10ep195, mc100ep195 http://onsemi.com 6 table 6. theoretical delay values d(9:0) value setmin setmax programmable delay* xxxxxxxxxx h l 0 ps 0000000000 l l 0 ps 0000000001 l l 10 ps 0000000010 l l 20 ps 0000000011 l l 30 ps 0000000100 l l 40 ps 0000000101 l l 50 ps 0000000110 l l 60 ps 0000000111 l l 70 ps 0000001000 l l 80 ps 0000010000 l l 160 ps 0000100000 l l 320 ps 0001000000 l l 640 ps 0010000000 l l 1280 ps 0100000000 l l 2560 ps 1000000000 l l 5120 ps 1111111111 l l 10230 ps xxxxxxxxxx l h 10240 ps *fixed minimum delay not included.
mc10ep195, mc100ep195 http://onsemi.com 7 0.0 1000.0 2000.0 3000.0 4000.0 5000.0 6000.0 7000.0 8000.0 9000.0 10000.0 11000.0 12000.0 13000.0 14000.0 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1000.0 delay ( ps) decimal value of select inputs (d[9:0]) 85 c ?40 c figure 4. measured delay vs. select inputs 25 c v cc = 0 v v ee = ?3.3 v table 7. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive mode power supply v ee = 0 v 6 v v ee negative mode power supply v cc = 0 v ?6 v v i positive mode input voltage negative mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ?6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm lqfp?23 lqfp?23 80 55 c/w c/w jc thermal resistance (junction?to?case) standard board lqfp?23 12 to 17 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm qfn?32 qfn?32 31 27 c/w c/w jc thermal resistance (junction?to?case) 2s2p qfn?32 12 c/w t sol wave solder pb?free <2 to 3 sec @ 260 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
mc10ep195, mc100ep195 http://onsemi.com 8 table 8. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 7) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee negative power supply current 100 145 175 100 150 180 100 150 180 ma v oh output high voltage (note 8) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 8) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (single?ended) lvpecl lvcmos lvttl 2090 2000 2000 2415 3300 3300 2155 2000 2000 2480 3300 3300 2215 2000 2000 2540 3300 3300 mv v il input low voltage (single?ended) lvpecl lvcmos lvttl 1365 0 0 1690 800 800 1430 0 0 1755 800 800 1490 0 0 1815 800 800 mv v bb ecl output voltage reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mv v cf lvttl mode input detect voltage 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 v v ef reference voltage for ecl mode connection 1920 2020 2120 1980 2080 2180 2030 2130 2230 mv v ihcmr input high voltage common mode range (differential configuration) (note 9) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current (@ v ih ) 150 150 150 a i il input low current (@ v il )in in 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?0.3 v. 8. all loading with 50 to v cc ? 2.0 v. 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 9 table 9. 10ep dc characteristics, necl v cc = 0 v, v ee = ?3.3 v to ?3.0 v (note 10) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee negative power supply current 100 145 175 100 150 180 100 150 180 ma v oh output high voltage (note 11) ?1135 ?1010 ?885 ?1070 ?945 ?820 ?1010 ?885 ?760 mv v ol output low voltage (note 11) ?1935 ?1810 ?1685 ?1870 ?1745 ?1620 ?1810 ?1685 ?1560 mv v ih input high voltage (single?ended) lvnecl ?1210 ?885 ?1145 ?820 ?1085 ?760 mv v il input low voltage (single?ended) lvnecl ?1935 ?1610 ?1870 ?1545 ?1810 ?1485 mv v bb ecl output voltage reference ?1510 ?1410 ?1310 ?1445 ?1345 ?1245 ?1385 ?1285 ?1185 mv v ef reference voltage for ecl mode connection ?1380 ?1280 ?1180 ?1320 ?1220 ?1120 ?1270 ?1170 ?1070 mv v ihcmr input high voltage common mode range (differential configuration) (note 12) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current (@ v ih ) 150 150 150 a i il input low current (@ v il )in in 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. input and output parameters vary 1:1 with v cc. v ee can vary +0.3 v to ?0.3 v. 11. all loading with 50 to v cc ? 2.0 v. 12. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 10 table 10. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 13) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee negative power supply current 100 135 160 100 140 170 100 145 175 ma v oh output high voltage (note 14) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 14) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mv v ih input high voltage (single?ended) lvpecl cmos ttl 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 mv v il input low voltage (single?ended) lvpecl cmos ttl 1305 0 0 1675 800 800 1305 0 0 1675 800 800 1305 0 0 1675 800 800 mv v bb ecl output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v cf lvttl mode input detect voltage 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 v v ef reference voltage for ecl mode connection 1920 2020 2120 1920 2020 2120 1920 2020 2120 mv v ihcmr input high voltage common mode range (differential configuration) (note 15) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current (@ v ih ) 150 150 150 a i il input low current (@ v il )in in 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. input and output parameters vary 1:1 with v cc. v ee can vary +0.3 v to ?0.3 v. 14. all loading with 50 to v cc ? 2.0 v. 15. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc. the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 11 table 11. 100ep dc characteristics, necl v cc = 0 v, v ee = ?3.3 v (note 16) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee negative power supply current (note 17) 100 135 160 100 140 170 100 145 175 ma v oh output high voltage (note 18) ?1145 ?1020 ?895 ?1145 ?1020 ?895 ?1145 ?1020 ?895 mv v ol output low voltage (note 18) ?1995 ?1820 ?1695 ?1995 ?1820 ?1695 ?1995 ?1820 ?1695 mv v ih input high voltage (single?ended) lvnecl ?1225 ?880 ?1225 ?880 ?1225 ?880 mv v il input low voltage (single?ended) lvnecl ?1995 ?1625 ?1995 ?1625 ?1995 ?1625 mv v bb ecl output voltage reference ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ef reference voltage for ecl mode con- nection ?1380 ?1280 ?1180 ?1380 ?1280 ?1180 ?1380 ?1280 ?1180 mv v ihcmr input high voltage common mode range (differential configuration) (note 19) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current (@ v ih ) 150 150 150 a i il input low current (@ v il )in in 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. input and output parameters vary 1:1 with v cc. v ee can vary +0.3 v to ?0.3 v. 17. recommended v cc ? v ee operation at 3.0 v 3.6 v. 18. all loading with 50 to v cc ? 2.0 v. 19. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 12 table 12. ac characteristics v cc = 0 v; v ee = ?3.0 v to ?3.6 v or v cc = 3.0 v to 3.6 v; v ee = 0 v (note 20) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max f max maximum frequency 1.2 1.2 1.2 ghz t plh t phl propagation delay in to q; d(0?10) = 0 in to q; d(0?10) = 1023 en to q; d(0?10) = 0 d0 to cascade 1650 9500 1600 300 2050 11500 2150 420 2450 13500 2600 500 1800 10000 1800 350 2200 12200 2300 450 2600 14000 2800 550 1950 10800 2000 425 2350 13300 2500 525 2750 15800 3000 625 ps t range programmable range t pd (max) ? t pd (min) 7850 9450 8200 10000 8850 10950 ps t step delay (note 21) d0 high d1 high d2 high d3 high d4 high d5 high d6 high d7 high d8 high d9 high 13 27 44 90 130 312 590 1100 2250 4500 14 30 47 97 140 335 650 1180 2400 4800 41 100 145 360 690 1300 2650 5300 ps mono monotonicity (note 27) tbd t skew duty cycle skew (note 22) |t phl ?t plh | 25 25 25 ps t s setup time d to len d to in (note 23) en to in (note 24) 200 300 300 0 140 150 200 300 300 0 160 170 200 300 300 0 180 180 ps t h hold time len to d in to en (note 25) 200 400 60 250 200 400 100 280 200 400 80 300 ps t r release time en to in (note 26) set max to len set min to len 150 400 350 ?25 200 275 150 400 350 ?75 250 200 150 400 350 ?50 300 225 ps t jitter rms random clock jitter @ 1.2 ghz in to q; d(0:10) = 0 or setmin in to q; d(0:10) = 1023 or setmax 0.86 0.89 1.16 1.09 1.12 1.02 ps v pp input voltage swing (differential configuration) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall time @ 50 mhz 20?80% (q) 20?80% (cascade) 85 100 100 140 135 200 85 110 110 150 135 200 95 130 125 170 155 220 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. 21. specification limits represent the amount of delay added with the assertion of each individual delay control pin. the variou s combinations of asserted delay control inputs will typically realize d0 resolution steps across the specified programmable range. 22. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 23. this setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 24. this setup time is the minimum time that en must be asserted prior to the next transition of in/in to prevent an output response greater than 75 mv to that in/in transition. 25. this hold time is the minimum time that en must remain asserted after a negative going in or positive going in to prevent an output response greater than 75 mv to that in/in transition. 26. this release time is the minimum time that en must be deasserted prior to the next in/in transition to ensure an output response that meets the specified in to q propagation delay and transition times. 27. the monotonicity indicates the increasing delay value for each binary count increment on the control inputs d[9:0].
mc10ep195, mc100ep195 http://onsemi.com 13 figure 5. ac reference measurement in in q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) cascading multiple ep195s to increase the programmable range of the ep195, internal cascade circuitry has been included. this circuitry allows for the cascading of multiple ep195s without the need for any external gating. furthermore, this capability requires only one more address line per added e195. obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. figure 6 illustrates the interconnect scheme for cascading two ep195s. as can be seen, this scheme can easily be expanded for larger ep195 chains. the d10 input of the ep195 is th e cascade control pi n. with the interconnect scheme of figure 6 when d10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin cascade high and pin cascade low. the a11 address can be added to generate a cascade output for the next ep195. for a 2?device configuration, a11 is not required. v ee d0 v cc q q nc v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf input outpu t v ee d0 v cc q q nc v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf ep195 chip #2 ep195 chip #1 address bus a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 need if chip #3 is used figure 6. cascading interconnect architecture
mc10ep195, mc100ep195 http://onsemi.com 14 an expansion of the latch section of the block diagram is pictured in figure 7. use of this diagram will simplify the explanation of how the cascade circuitry works. when d10 of chip #1 in figure 6 is low this device?s cascade output will also be low while the cascade output will be high. in this condition the set min pin of chip #2 will be asserted high and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. chip #1, on the other hand, will have both set min and set max deasserted so that its delay will be controlled entirely by the address bus a0?a9. if the delay needed is greater than can be achieved with 1023 gate delays (1111111111 on the a0?a9 address bus) d10 will be asserted to signal the need to cascade the delay to the next ep195 device. when d10 is asserted, the set min pin of chip #2 will be deasserted and set max pin asserted resulting in the device delay to be the maximum delay. table 13 shows the delay time of two ep195 chips in cascade. to expand this cascading scheme to more devices, one simply needs to connect the d10 pin from the next chip to the address bus and cascade outputs to the next chip in the same manner as pictured in figure 6. the only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. set min set max to select multiplexers bit 0 d0 q0 len set reset bit 1 d1 q1 len set reset bit 2 d2 q2 len set reset bit 3 d3 q3 len set reset bit 4 d4 q4 len set reset bit 5 d5 q5 len set reset bit 6 d6 q6 len set reset bit 7 d7 q7 len set reset bit 8 d8 q8 len set reset bit 9 d9 q9 len set reset figure 7. expansion of the latch section of the ep195 block diagram
mc10ep195, mc100ep195 http://onsemi.com 15 table 13. delay value of two ep195 cascaded variable input to chip #1 and setmin for chip #2 input for chip #1 total d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 delay value delay value 0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps 0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps 0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps 0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps 0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps 0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps 0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps 0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps 0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps 0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps 0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps 0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps 0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps 0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps 0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps 0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps variable input to chip #1 and setmax for chip #2 input for chip #1 total d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 delay value delay value 1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps 1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps 1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps 1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps 1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps 1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps 1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps 1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps 1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps 1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps 1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps 1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps 1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps 1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps 1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps 1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps
mc10ep195, mc100ep195 http://onsemi.com 16 multi?channel deskewing the most practical application for ep195 is in multiple channel delay matching. slight differences in impedance and cable length can create large timing skews within a high?speed system. to deskew multiple signal channels, each channel can be sent through each ep195 as shown in figure 8. one signal channel can be used as reference and the other ep195s can be used to adjust the delay to eliminate the timing skews. nearly any high?speed system can be fine?tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances. ep195 in q in q #1 ep195 in q in q #2 ep195 in q in q #n digital data control logic figure 8. multiple channel deskewing diagram measure unknown high speed device delays ep195s provide a possible solution to measure the unknown delay of a device with a high degree of precision. by combining two ep195s and ep31 as shown in figure 9, the delay can be measured. the first ep195 can be set to setmin and its output is used to drive the unknown delay device, which in turn drives the input of a d flip?flop of ep31. the second ep195 is triggered along with the first ep195 and its output provides a clock signal for ep31. the programmed delay of the second ep195 is varied to detect the output edge from the unknown delay device. if the programmed delay through the second ep195 is too long, the flip?flop output will be at logic high. on the other hand, if the programmed delay through the second ep195 is too short, the flip?flop output will be at a logic low. if the programmed delay is correctly fine?tuned in the second ep195, the flip?flop will bounce between logic high and logic low. the digital code in the second ep195 can be directly correlated into an accurate device delay. ep195 in q in q #1 ep195 in q in q #2 unknown delay device control logic d clk q q ep31 clock clock figure 9. multiple channel deskewing diagram
mc10ep195, mc100ep195 http://onsemi.com 17 figure 10. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? mc10ep195fag lqfp?32 (pb?free) 250 units / tray mc10ep195far2g lqfp?32 (pb?free) 2000 / tape & reel mc10ep195mng qfn?32 (pb?free) 74 units / rail mc10ep195mnr4g qfn?32 (pb?free) 1000 / tape & reel mc100ep195fag lqfp?32 (pb?free) 250 units / tray mc100ep195far2g lqfp?32 (pb?free) 2000 / tape & reel mc100ep195mng qfn?32 (pb?free) 74 units / rail mc100ep195mnr4g qfn?32 (pb?free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc10ep195, mc100ep195 http://onsemi.com 18 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ?t? ?z? ?u? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t-u m 0.20 (0.008) z ac 32 lead lqfp case 873a?02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
mc10ep195, mc100ep195 http://onsemi.com 19 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc10ep195/d eclinps is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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